Low latency Data Mover implements bidirectional data movements between the host and FPGA with approximately 600ns of latency in each direction.
Pushing data and status/control information across the PCIe link using cut-through techniques
Does not rely on a traditional direct memory access (DMA) engine performing store-and-forward buffer transfers with status/scoreboard updates
Streaming sideband identifiers: start-of-packet (SOP), end-of-packet (EOP), and the number of valid bytes within the stream of data are encoded into the address space of the FIFO to improve transfer efficiency
Payloads are buffered internally along with status information such as SOP and EOP from the Avalon-ST sink interface that user logic interfaces with
Mixture of payload and status information is then interleaved with synchronization information
Consume the payload and status information as it arrives instead of waiting for entire packets to arrive
A low-level user space driver is provided to expose direct access to the interleaved payload, status, and synchronization information as well as APIs to access deinterleaved payloads.”

Ultra-Low-Latency (ULL) PHY+MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. Algo-Logic Systems’ ULL PHY+MAC design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in FPGA fabric optimized for latency.
Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet
Local fault and remote fault detection
Frame Check Sequence (FCS) insertion and verification at line rate
Automatic transmit padding, jumbo frame support, transmit and receive statistics counters

TCP Endpoint implements a reliable streaming network stack in FPGA logic. It allows applications in logic to be directly connected to Internet Protocol (IP) endpoints by opening, maintaining, and closing TCP Connections via Ethernet.
Ultra-low latency
RTL design for optimal performance
Optional cut-through for receive (RX) and transmit (TX) data
Parameters
Retransmission timeouts
Size of shared on-chip retransmission buffer
Option for fast retransmission
Limits on retransmissions
TX Rewind