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How to achieve Ultra Low Latency Networking with Algo-Logic on the Intel PAC D5005 FPGA Card

How to Achieve

Ultra-Low Latency (ULL) Networking

Tick-to-Trade Reference Design 

Perspectives on HLS from a Sr. Software Developer (Slides)

Algo-Logic's ULL Framework for Intel PAC D5005

Tick-to-Trade Demo

Perspectives on HLS from a Sr. Software Developer (Demo)


Following on from Algo-Logic’s innovation round-up of the same title at the recent STAC conference, Algo-Logic offers this webinar to dive deeper into the highly competitive and rapidly evolving market where latency is everything. By leveraging Intel's FPGA and tools with Algo-Logic's Framework, you can migrate latency sensitive portions of you workload from software into an FPGA hardware thereby reducing your trading latency. While historically this migration has been technically daunting due to the complexity of programming FPGAs, the Algo-Logic Framework along with the Intel HLS tools are lowering the barriers and reducing the technical risks.

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