Agenda
  1. How to Achieve Ultra-Low Latency(ULL) Networking

  2. Algo-Logic's ULL Framework for Intel PAC D5005

  3. Tick-to-Trade Reference Design

    • Reference Design​

    • T2T Demo

  4. Perspectives on HLS from a Sr. Software Developer

    • Slides​

    • Demo

  5. Conclusions

Following on from Algo-Logic’s innovation round-up of the same title at the recent STAC conference, Algo-Logic offers this webinar to dive deeper into the highly competitive and rapidly evolving market where latency is everything. By leveraging Intel's FPGA and tools with Algo-Logic's Framework, you can migrate latency sensitive portions of you workload from software into an FPGA hardware thereby reducing your trading latency. While historically this migration has been technically daunting due to the complexity of programming FPGAs, the Algo-Logic Framework along with the Intel HLS tools are lowering the barriers and reducing the technical risks.

For more information email us at: IntelSupport@Algo-Logic.com