Development Framework
Algo-Logic has partnered with leading FPGA vendors to provide a development framework designed to allow customers who require the performance and power consumption advantages of FPGA technology but who do not have hardware expertise within their development teams.
The Algo-Logic FPGA Development Framework provides a FPGA platform that includes Ultra-Low Latency 10GbE MAC, TCP Endpoint, PCIe Host Interface, and a Business Strategy Block for High Level Synthesis (HLS) implementation. To this basic Framework we can add the EMSE / Key Value Store (KVS) and UDP engine IP Cores to create an Enhanced Framework. With these additions you can store and access large data sets in a KVS or parse Ethernet Packets including Exchange Market Data in HLS.
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If you have an application that would benefit from FPGA Acceleration but you have been reluctant to jump in due to the large technical challenge, the Algo-Logic FPGA Development Framework provides a fast path to FPGA implementation.
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Key Benefits
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Very low latency performance
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Deterministic performance which virtually eliminates jitter
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All Key Ethernet, TCP, and PCIe Host IP Blocks already in place
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Your design effort is focused on HLS which is similar to C/C++
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The FPGA development environment is in place on the Algo-Logic Cloud
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Development is flexible either Algo-Logic design services or as needed support to your team
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Frameworks