Intel PAC D5005 Framework

The Algo-Logic Framework is a general purpose system designed to not only excel in Ultra-Low Latency HFT Trading or Pre-Trade Risk Check systems that benefit from FPGA Acceleration but also to a wide range of non-Financial Trading applications.

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Low latency Data Mover implements bidirectional data movements between the host and FPGA with approximately 600ns of latency in each direction.

• Pushing data and status/control information across the PCIe link using cut-through techniques

• Does not rely on a traditional direct memory access (DMA) engine performing store-and-forward buffer transfers with status/scoreboard updates

• Streaming sideband identifiers: start-of-packet (SOP), end-of-packet (EOP), and the number of valid bytes within the stream of data are encoded into the address space of the FIFO to improve transfer efficiency

• Payloads are buffered internally along with status information such as SOP and EOP from the Avalon-ST sink interface that user logic interfaces with

• Mixture of payload and status information is then interleaved with synchronization information

• Consume the payload and status information as it arrives instead of waiting for entire packets to arrive

• A low-level user space driver is provided to expose direct access to the interleaved payload, status, and synchronization information as well as APIs to access deinterleaved payloads."