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  • Ultra-low-latency  round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit

  • Reconciliation sub-layer implementation compliant with IEEE802.3

  • Local fault and remote fault detection and handling

ULL 10GbE MAC.png

Key Features

  • Frame Check Sequence (FCS) insertion and verification at line rate

  • Automatic transmit padding, jumbo frame support, transmit and receive statistics counters

  • Compatible with multiple FPGA platforms as soft-logic around SERDES

    • Supports both standard Avalon-ST / AXI4-Stream bus interfaces

    • Direct replacement for high-latency default vendor cores

  • High level architecture Ethernet MAC design is flexible in its use of system clock (on the Avalon ST side)

  • Optimized for HFT Trading Solutions and PTRC systems

  • Low gate count

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