Supermicro, AMD, and Algo-Logic Deliver Ultra-Low-Latency (ULL) Solution for High Frequency Trading
October 2026
EXECUTIVE SUMMARY
Ultra-Low Latency (ULL) trading systems enable traders to react instantly to changing market conditions and place orders on an exchange. Similar trading strategies implemented on slower servers miss opportunities and have orders “picked off” by faster
competitors. Latency is a key metric at all levels of the trading system. This paper describes a reference server optimized for trading that minimizes latency across four levels of the system:
The most latency-sensitive portion of the tick-to-trade algorithm is implemented entirely in hardware. For this, the entire datapath from market data input to order output is implemented using Algo-Logic gateware running on a Field Programmable Gate Array (FPGA).
The next-lowest level of latency minimizes the time required to communicate between user-space software and the FPGA. For this, messages are sent using an AMD/Solarflare X4 NIC that bypasses the operating system kernel.
For trading algorithms that require use of parallel CPU cores, we characterize the latency between cores through memory using the MLC benchmark on multiple AMD EPYCTM CPUs.
Finally, for logging and compliance, we measure file Input/Output (I/O) for trade events using the fio benchmark.
Supermicro, AMD, and Algo-Logic together provide the key elements and technologies necessary to deliver performance-optimized ULL trading systems. In this paper, we characterize Supermicro AS -2015HS-TNR Server equipped with AMD’s EPYC processors, AMD Xilinx Field Programmable Gate Array (FPGA) accelerators, and AMD Solarflare’s high-performance X4 Ethernet
NICs. On the FPGA, we run Algo-Logic’s gateware (logic gates that run on the FPGA) to implement an Ultra-Low-Latency Tick-to-Trade system. Combined, these technologies deliver a competitive edge to ULL trading firms. A diagram of the combined reference system is shown below:
TICK2TRADE SERVER:
SUPERMICRO AS -2015HS-TNR SERVER
The Supermicro Hyper AS -2015HS-TNR server is engineered to deliver deterministic, high-throughput compute and low-latency I/O for mission-critical financial market infrastructure. Built around a single-socket architecture supporting the AMD EPYC 9005/9475F series processors in an SP5 socket, the AS -2015HS-TNR eliminates NUMA cross-socket interconnect latency (xGMI/UPI hops) by routing 128 PCIe® Gen 5.0 lanes directly from the processor root complex to high-density expansion slots.
To support sustained, deterministic packet processing under high-burst market data conditions, the Supermicro AS -2015HS-TNR server features an enterprise 2U thermal design with optimized fan curves and redundant titanium-level power supplies.
This ensures high-TDP, high-boost trading processors and low-latency network accelerators—such as the AMD SolarflareTM X4522-PLUS—operate well within thermal operating margins without frequency throttling or jitter. With support for up to 12 channels of DDR5 memory and flexible PCIe Gen 5 riser configurations, the AS -2015HS-TNR combines the latency determinism of a single-socket system with enterprise-grade serviceability, remote out-of-band management (Redfish/IPMI), and turnkey deployment across global trading co-location facilities.
FPGA ACCELERATION
Ultra-low latency is achieved by performing time-critical packet processing operations in FPGA logic. Algo-Logic’s gateware accelerates market data processing and order sending by offloading the UDP/IP and TCP/IP networking stacks onto hardware and implementing the core trading functions in logic. Combined, the server trades deterministically and with significantly lower latency than by running trading functions only in software.
ALGO-LOGIC’S TICK TO TRADE GATEWARE
Algo‐Logic’s Tick‐to‐Trade (T2T) gateware runs inside the AMD/Xilinx UltraScale+ FPGA and consistently delivers lower latency than Order Management System (OMS) software running on a CPU. Algo‐Logic’s FPGA Gateware executes the entire T2T pipeline in hardware circuits, delivering T2T trading latency in a fraction of a microsecond with no long‐tail outliers. The deterministic logic avoids jitter, which avoids the statistical odds of executing a delayed trade.
As shown above, Algo‐Logic’s gateware (the logic that runs on the FPGA) accelerates time-critical trading algorithms. The logic receives market data as redundant A and B packets via Ultra Low Latency MACs, processes those feeds, maintains order books, evaluates triggers to implement a strategy, prepares the order for execution, and then sends those orders to the exchange over the network using TCP/IP packets in Ethernet frames. Rather than running in software, Algo‐Logic’s gateware executes the entire time-critical aspect of the trade in hardware logic, providing the lowest possible latency path.
The control interface (shown at the top-left of the diagram) allows strategies to be preloaded and controlled from host software while trade logic executes deterministically in hardware. This gives firms both flexibility and the ability to execute
trades immediately. Ease of use of the software, combined with a complete hardware data path, is the primary reason Algo-Logic’s T2T solution is superior to other offerings that only accelerate isolated components such as market data parsing or risk checks.
In short, the Algo-Logic T2T FPGA implementation isn’t just significantly faster than software; it is architecturally aligned with the demands of modern ULL electronic markets. It provides predictable timing, parallel processing, and custom pipelines that
enable the ULL system to operate at the physical limits of network and exchange latency.
For the system described in this paper, the external latency for sending orders to the CME exchange via an iLInk order session in response to either the A or B market data feed, including the processing of the order book, the strategy block implemented with High Level Synthesis (HLS), the order execution including message processing, the TCP/IP network stack, and the Ultra-Low-Latency MAC was externally measured to be less than a microsecond. For certain trades, the tick-to-trade latency can be as low as 180ns.
FPGA ACCELERATOR: AMD/XILINX VU5P FPGA
Trade acceleration was implemented using the AMD Ultrascale+ FPGA mounted on a PCIe Express card mounted in the rack-mount server. By default, Algo-Logic runs the T2T on a Cisco Nexus V5P with the AMD/Xilinx VU5P FPGA device. Algo-Logic also supports the faster VU2P on the AMD/Xilinx X3524 Adapter. Communication with the hosts was performed using registers mapped across the PCIe bus, as well as messages sent to the hosts via a kernel-bypass NIC.
ONLOAD NETWORK INTERFACE CARDS (NIC): AMD SOLARFLARE
For software interactions, the best practice is to allow user-space processes to communicate directly with the network adapter hardware. Solarflare NICs paired with Onload have been widely used in capital markets for over 15 years because
their technology enables single-digit microsecond latency for electronic trading workloads. On this system, the latest AMD Solarflare X4 NIC is used to provide kernel‐bypass messaging between the trade logic and the FPGA hardware.
Instead of routing packets through the Linux kernel’s traditional networking path—where interrupts, context switches, and buffer copies can introduce delays—Onload allows applications to send and receive packets directly through the NIC’s hardware. The Onload NIC, coupled with FPGA hardware, enables trading systems to update hardware trigger parameters quickly. Latency between CPU cores for parallel computing
The third tier of system latency concerns the time required to communicate via memory between CPU cores. For example, when trading options, parallel computation across many CPU cores is used to compute theoretical option prices, which are then used to execute trades. Lower latency yields faster price updates.
MEMORY LATENCY CHECKER (MLC)
The Memory Latency Checker (MLC) tool characterizes how well the hierarchy of system memory behaves under load. It characterizes local vs. remote Non-Uniform Memory Access (NUMA) latency, bandwidth ceilings, caching behavior, and overall performance with mixed read and write operations. MLC exposes latency when CPU threads touch memory and under realistic pressure.
The MLC benchmark measures how latency balloons when bandwidth saturates, when read/write mixes shift, or when multiple cores hammer the same node. This is especially important in architectures with high core counts or asymmetric memory channels.
In this paper, we measured latencies of two recent AMD EPYC CPUs. The results are below.
As shown above, the AMD EPYC 9575F achieves lower (better) minimum memory latency than the previous-generation AMD EPYC 9474F. Furthermore, the AMD EPYC 9575F achieves higher (better) peak injection memory bandwidth than the 9474F with all
cores busy.
FLEXIBLE I/O TESTER (FIO)
The Flexible I/O Tester (fio) tool was used to characterize the behavior of the Input/Output subsystem under load. It characterized performance for varied block sizes, queue depths, read/write mixes, and threading models. For this paper, we characterize workloads most relevant for trading, specifically workloads for logging data to shared memory and NVMe storage.
Complex trading applications use multiple threads, processes, and services that access the same device simultaneously. fio uncovers NUMA effects, PCIe bottlenecks, and filesystem quirks that only appear under load. For this test, we measured two recent AMD EPYC CPUs. The results are below.
As shown above, we compared the fio performance of the AMD EPYC 9474F and 9575F CPUs while writing to shared memory (/dev/shm). For a single thread with 4KB to 1MB writes, the 9575F achieved higher throughput, and likewise for 16 threads with 64KB writes, the 9595F also achieved higher (better) throughput. The performance improvement was even more significant with three streams, which was the typical load for trading workload.
MLC and fio matter for ULL trading because they highlight different latency domains, both of which are critical for ultra‐low‐latency trading. The hot path of core-to-core communication is governed by memory locality, cache behavior, and CPU topology, as characterized by MLC. The warm path for logging, persistence, drop‐copy, surveillance, and post‐trade analytics, which factors in storage throughput, IOPS stability, and tail‐latency behavior, was characterized by fio.
THE SUPERMICRO AS-2015CS-TNR SERVER
Readily suitable for deployment in co-located trading environments, the 2U rack-mount server was used to implement the rack-mount server. The system included 12 DDR5 DIMM modules, 12 3.5” drive bays, and an SP5 socket for the AMD EPYC CPUs.
CONCLUSION
ULL trading emphasizes high‐frequency processors, paired with ultra‐low‐latency FPGAs and low-latency NICs, along with precision Gateware to deliver low-latency, high-throughput performance under all conditions, even when markets are changing
rapidly.
Together, the solution with Supermicro AS-2015CS-TNR Server, Algo-Logic T2T Gateware System, AMD EPYC 9575F processor, AMD Solarflare X4 NIC, and AMD Xilinx FPGA-based system delivers extremely low round‐trip times ideal for ULL execution paths,
and is a compelling choice for firms building modern, low‐latency trading systems.
SUPERMICRO
As a global leader in high performance, high efficiency server technology and innovation, we develop and provide end-to-end green computing solutions to the data center, cloud computing, enterprise IT, big data, HPC, and embedded markets. Our Building Block Solutions® approach allows us to provide a broad range of SKUs, and enables us to build and deliver application-optimized solutions based upon your requirements.
Visit: www.supermicro.com
AMD
AMD (NASDAQ: AMD) drives innovation in high-performance and AI computing to solve the world’s most important challenges. Today, AMD technology powers billions of experiences across cloud and AI infrastructure, embedded systems, AI PCs and gaming.
With a broad portfolio of AI-optimized CPUs, GPUs, networking and software, AMD delivers full-stack AI solutions that provide the performance and scalability needed for a new era of intelligent computing.
Visit: www.amd.com
ALGO-LOGIC
Algo-Logic Systems is a recognized leader that provides gateware to implement full Tick-to-Trade (T2T) trading solutions. Algo-Logic maps algorithms into logic that runs on Field Programmable Array (FPGA) devices. Algo-Logic’s Gateware Defined Networking (GDN) libraries feature proven IP cores for Ultra Low Latency (ULL) Ethernet, UDP/IP and TCP/IP packet processing in logic, and libraries to process market data and send orders for major equity, commodity, and option markets.
Visit: www.algo-logic.com
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